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Lead verification of complex SoC and FPGA subsystems using constrained-random, formal and C-based methods. Develop reusable UVM testbenches, integrate AI/ML verification tools, collaborate with emulation/prototyping and architecture teams, and mentor junior engineers to ensure first-silicon success.

Design and maintain reusable UVM-based testbenches and verification environments for next-generation secure, low-power FPGAs. Perform constrained-random, formal and C-based verification, RTL and power-aware verification, collaborate with emulation, prototyping, architecture and design teams, and apply AI/ML-enabled verification techniques to improve coverage and productivity.

Provide technical solutions for hardware, software, and manufacturing issues across product development. Create documentation, training, and proofs-of-concept. Collaborate with quality, sales, and business units to improve product quality and resolve client issues, and support clients on embedded and connectivity technologies from concept through production.

The Principal Engineer will develop RTL for digital IP blocks, optimize performance and area, and collaborate with teams on system validation and verification efforts.

Design analog and mixed-signal circuits, simulate designs with CAD tools, guide layout designers, validate silicon performance, and document results.

Develop and maintain embedded software and peripheral drivers for RISC-V SoC FPGAs, collaborate on silicon bring-up and debugging, create reference designs and examples, and resolve technical issues with silicon engineering and validation teams.