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Design and implement complex digital ASIC IP using SystemVerilog, optimize power, performance, and area, and collaborate on SoC integration and physical design closure. Lead lint, CDC, RDC, formal verification, timing, and routing efforts. Support module and system validation, post-silicon bring-up, lab testing, and design documentation.

Design, characterize, test, qualify, and support production of MEMS timing devices and resonators. Perform simulations, laboratory evaluations, debugging, data analysis, and root-cause investigations. Develop test software and automation, collaborate with MEMS, ASIC, fabrication, assembly, quality, and product engineering teams, and communicate technical findings and project status throughout the product lifecycle.

Develop and maintain embedded software and peripheral drivers for RISC-V SoC FPGAs, collaborate on silicon bring-up and debugging, create reference designs and examples, and resolve technical issues with silicon engineering and validation teams.

Lead verification of complex SoC and FPGA subsystems using constrained-random, formal and C-based methods. Develop reusable UVM testbenches, integrate AI/ML verification tools, collaborate with emulation/prototyping and architecture teams, and mentor junior engineers to ensure first-silicon success.

Design and maintain reusable UVM-based testbenches and verification environments for next-generation secure, low-power FPGAs. Perform constrained-random, formal and C-based verification, RTL and power-aware verification, collaborate with emulation, prototyping, architecture and design teams, and apply AI/ML-enabled verification techniques to improve coverage and productivity.