ABOUT ARAGO
The demand for more intelligence continues to accelerate in every industry, application, and device. Yet, general-purpose processors cannot take us much farther. To unlock the next breakthroughs, Arago is developing a processor that harnesses the unique physical properties of light to address both memory and computational limitations.
We are a team of AI engineers and physicists who believe in great science and fast achievements. We’re looking for bold jack-of-all-trades who love to ship products quickly.
Our team is driven by these core values:
Do great things: We’re going after a 10x, not 10%. It requires intensity, craftsmanship, and great science.
We move as one: Our relationships are built on trust and mutual admiration. We feel empowered and fortunate to collaborate with one another.
Keep looking ahead: Lasting technologies and impactful ventures are not built overnight. We take it one step at a time, with velocity.
ROLE OVERVIEW
As a Digital Backend Design Engineer, you will be responsible for the physical implementation of digital designs from RTL to GDSII, leveraging cutting-edge EDA tools and methodologies. You will collaborate closely with RTL design, DFT, and packaging teams to achieve optimal performance, power, and area (PPA), while meeting stringent timing and yield targets on the GF22 FDX+ node.
KEY RESPONSIBILITIES
Execute full-chip and block-level physical design tasks including floorplanning, placement, clock tree synthesis, routing, and physical verification.
Develop and optimize the digital backend flow tailored for the GF22 FDX+ process.
Drive timing closure, power optimization, and physical verification (LVS/DRC/ERC).
Collaborate with front-end designers to address timing and logical/physical interface issues.
Support tapeout preparation and final signoff processes.
REQUIRED QUALIFICATIONS
Master’s or PhD degree in Electrical/Electronic Engineering or a related field.
4+ years experience in digital IC backend implementation.
Proficiency with backend EDA tools, particularly Cadence Innovus and Genus.
Strong understanding of place & route (P&R), static timing analysis (STA), DRC/LVS verification, IR drop, and electromigration (EM) analysis.
Experience with advanced technology nodes (22nm or below preferred).
Familiarity with the GF22 FDX+ process is highly advantageous.
Skilled in Tcl scripting for automation of backend flows.
Experience in hierarchical or full-chip implementation is preferred.
REWARDS & PERKS
Competitive cash compensation that reflects your expertise and experience.
Stock options.
Ownership of a key technical area.
Being part of the early stage of one of the hottest AI startups (currently in stealth mode).
A fun, dynamic, and multicultural team in a collaborative environment.
Exciting professional growth opportunities.
SELECTION PROCESS
CV and technical project review.
45-minute interview with the CEO.
Take-home technical assignment.
1-hour technical interview with the CTO, CSO, CEO, and potential team members.
.png)
